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Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
MegaWizard Plug-In Manager Design Flow
You can use the MegaWizard Plug-In Manager in the Quartus II software to
parameterize a custom IP core variation. When you select the RapidIO IP core in the
MegaWizard Plug-In Manager, the RapidIO parameter editor appears. The RapidIO
parameter editor lets you interactively set parameter values and select optional ports.
This flow is best for manual instantiation of an IP core in your design.
Qsys Design Flow
The Qsys design flow enables you to integrate a RapidIO endpoint in a Qsys system.
The Qsys design flow allows you to connect component interfaces with the system
interconnect, eliminating the requirement to design low-level interfaces and
significantly reducing design time. When you add a RapidIO IP core instance to your
design, a RapidIO parameter editor guides you in selecting the properties of the
RapidIO IP core instance.
MegaWizard Plug-In Manager Design Flow
The MegaWizard Plug-In Manager flow allows you to customize the RapidIO IP core,
and manually integrate the function in your design.
Specifying Parameters
To specify RapidIO IP core parameters using the MegaWizard Plug-In Manager,
follow these steps:
1. Create a Quartus II project using the New Project Wizard available from the File
menu.
2. Launch the MegaWizard Plug-In Manager from the Tools menu, and follow the
prompts in the MegaWizard Plug-In Manager interface to create a custom
megafunction variation.
1
To select the RapidIO IP core, click
I nstalled Plug-Ins > Interfaces > RapidIO .
3. Specify the parameters on all pages in the Parameter Settings tab. For details
4. If you want to generate an IP functional simulation model for the IP core in the
selected language, on the EDA tab, turn on Generate simulation model .
The IP functional simulation model is a cycle-accurate VHDL or Verilog HDL
model produced by the Quartus II software.
c Use the simulation models only for simulation and not for synthesis or any other
purposes. Using these models for synthesis creates a nonfunctional design.
5. Some third-party synthesis tools can use a netlist that contains the structure of this
IP core but no detailed logic to optimize timing and performance of the design
containing it.
To use this feature if your synthesis tool supports it, turn on Generate netlist .
RapidIO MegaCore Function
User Guide
May 2013 Altera Corporation
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